Patent document 1, i.e., Japanese Patent No. 2014-30125, discloses a communication system in which two or more nodes connected to a transmission line perform data communication by using a line code of pulse width modulation (PWM) signals in two types with respectively different durations (i.e., continuation time) for a low level time (i.e., a duration of time in which a signal is in or at a low level). PWM is an abbreviation for pulse width modulation.
The communication system of the patent document 1 has the following requirements.
When a high level signal and a low level signal are simultaneously output from the different nodes on the transmission line, the signal level of the transmission line is set to the low level. That is, on the transmission line, priority is given to the low level signal over the high level signal.
The PWM signal as a line code changes from a high level as the first level to low level as the second level at a boundary of a bit. The PWM signal as a line code also changes from a low level to a high level in the middle of a bit. Further, the “logical value 1” and the “logical value 0” are distinguished by a different duration for low level time in a PWM signal, i.e., “a low level time.” For example, from among two types of PWM signals respectively having a different low level time, a PWM signal with a shorter low level time (i.e., the first PWM signal) corresponds to a “logical value 1”, and a PWM signal with a longer low level time (i.e., the second PWM signal) corresponds to a “logical value 0.”
One of two or more nodes on the transmission line is a master node which supplies a clock signal to the other nodes via the transmission line. The dock signal supplied by the master node is an edge at which the signal level of the transmission line changes from a high level to a low level, i.e., the edge corresponding to the boundary of a bit. Therefore, a master node outputs one of the first PWM signal and the second PWM signal to the transmission line. Note that, even in a no-data transmission period, a master node continues to output the first PWM signal to the transmission line in order to supply a clock signal to other nodes.
From among a plurality of two or more nodes on the transmission line, nodes other than the master node serve as slave nodes, to which a dock signal is supplied from the master node via the transmission line. When outputting the second PWM signal to the transmission line (i.e., when transmitting a “logical value 0”), the slave node starts a signal output operation of the second PWM signal when a high-to-low signal level change of the transmission line due to a signal output operation of the master node is detected.
In the communication system described above, there may be difficulties in increasing the communication speed. Such difficulties may be described in reference to FIGS. 12A and 12B.
In the illustration of FIGS. 12A and 12B, time t1 and time t2 respectively designate a timing of the boundary of a bit, or rather “a bit boundary.”
TXm is a signal input to a transmission buffer of a master node. TXs is a signal input to a transmission buffer of a slave node. In this example, the transmission buffer performs a signal output operation for changing the signal level of the transmission line from a high level to a low level, while the signal input to the transmission buffer is (i.e., stays) in a low level. Further, a low level time Tm1 of TXm is a low level time in which the master node outputs the first PWM signal to the transmission line, and a low level time Ts0 of TXs is a low level time in which the slave node outputs the second PWM signal to the transmission line.
Vth is a threshold used to determine whether the signal level of the transmission line is in a high level or in a low level in each of the master node and the slave node.
FIG. 12A shows a situation in which a time constant of the transmission line takes a minimum value of a specification range, i.e., “a specification minimum.” FIG. 12B shows a situation in which a time constant of the transmission line takes a maximum value of the above-mentioned specification range i.e., “a specification maximum.” The time constant of the transmission line changes at least according to the number of the nodes connected to the transmission line.
As shown in FIGS. 12A and 12B, after TXm changes to a low level, i.e., after the first PWM signal begins to be output at a low level by the master node, a certain time delay caused by the time constant of the transmission line is observed until the signal level of the transmission line changes to a low level.
Therefore, the low level time Tm1 of TXm is set as a duration of time that enables the signal level of the transmission line to be changed to a low level, even when the time constant of the transmission line takes the specification maximum, as shown in FIG. 12B.
On the other hand, as shown in FIG. 12A and FIG. 12B, when TXs changes to low level, i.e., at a time when the slave node starts to output the second PWM signal at a low level, the signal level of the transmission line falls to the threshold Vth due to the signal output operation of the master node.
Further, the low level time Ts0 of TXs is set to a longer duration than a time Ta required for TXm to return to a high level after TXs changes to a low level. In such cases, the duration of Ts0 is greater than or equal to the sum of Ta and a preset specification time RT, e.g., Ts0≥Ta+RT. Such a setting is required because it is necessary to provide a difference between the low level time of the first PWM signal and the low level time of the second PWM signal, which needs to be equal to or greater than the preset specification time RT. Note that the time around Ta is a time where both of the master node and the slave node change the transmission line to a low level. In the following, the time Ta is designated as a duplex output time Ta. Further, in FIGS. 12A and 12B, the waveform of the dashed-dotted line represents a signal waveform of the transmission line when only the master node outputs the first PWM signal, that is, without an output of the second PWM signal from the slave node.
Here, as readily seen from a comparison between FIGS. 12A and 12B, the smaller the time constant of the transmission line is, the shorter a time Tb, where Tb is the time from when TXm begins to fall from a high level to a low level to when TXs begins to fall to a low level. The decrease in the duration of Tb increases the duration of the duplex output time Ta. Therefore, the low level time Ts0 of TXs is set as a duration equal to or longer than the duplex output time Ta when the time constant of the transmission line takes the specification minimum, as shown in FIG. 12A. Note that, in FIG. 12A and FIG. 12B, the low level time Tm1 of TXm has the same duration, and the low level time Ts0 of TXs has the same duration.
However, as shown in FIG. 12B, compared to a time when the time constant of the transmission line increases to the specification maximum, the duplex output time Ta becomes shorter when the time constant of the transmission line is set to the specification minimum. As such, as shown in FIG. 12B, the difference between the low level time Tm1 of the first PWM signal and the low level time Ts0 of the second PWM signal is greater than the preset specification time RT, meaning that the amount of low level time Ts0 is excessive.
Therefore, when a transmission speed increases and a bit length shortens, a bit error, e.g. a bit “straddling” or “shortfall”, may occur as shown in FIG. 12B, where the signal level of the transmission line does not return to a high level by time t2, that is, before a bit boundary timing of the next bit, which may corrupt the data communication and/or cause additional communication errors. Such a problem may be more noticeable when the signal on the transmission line rises to a high potential level from a low potential level.